M. Winzker, P. Pirsch, J. Reimers, "Architecture and Memory Requirements for stand-alone and hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMs," IEEE International Symposium on Circuits and Systems, pp. 609-612, 1995.

Abstract

The architecture of dedicated MPEG2 HDTV-decoders for stand-alone and hierarchical transmission has been investigated. The high demands on the video memory in terms of memory capacity and data rate are met by using synchronous DRAMs and adapting the data accesses to the properties of the memory devices. Thus compact implementations for consumer and professional decoders become possible.